diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 12dc03c..2ac6b87 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -154,6 +154,7 @@
 	bool "Support P2041RDB"
 	select ARCH_P2041
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
+	select FSL_CORENET
 	select PHYS_64BIT
 	imply CMD_SATA
 	imply FSL_SATA
@@ -233,6 +234,7 @@
 config TARGET_KMCENT2
 	bool "Support kmcent2"
 	select VENDOR_KM
+	select FSL_CORENET
 
 endchoice
 
@@ -240,6 +242,7 @@
 	bool
 	select E500MC
 	select E6500
+	select FSL_CORENET
 	select FSL_LAW
 	select HETROGENOUS_CLUSTERS
 	select SYS_FSL_DDR_VER_47
@@ -268,6 +271,7 @@
 	bool
 	select E500MC
 	select E6500
+	select FSL_CORENET
 	select FSL_LAW
 	select HETROGENOUS_CLUSTERS
 	select SYS_FSL_DDR_VER_47
@@ -607,6 +611,7 @@
 	bool
 	select BACKSIDE_L2_CACHE
 	select E500MC
+	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_44
@@ -638,6 +643,7 @@
 	bool
 	select BACKSIDE_L2_CACHE
 	select E500MC
+	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_44
@@ -678,6 +684,7 @@
 	bool
 	select BACKSIDE_L2_CACHE
 	select E500MC
+	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_44
@@ -710,6 +717,7 @@
 	select BACKSIDE_L2_CACHE
 	select E500MC
 	select E5500
+	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
@@ -735,6 +743,7 @@
 	select BACKSIDE_L2_CACHE
 	select E500MC
 	select E5500
+	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
@@ -760,6 +769,7 @@
 	select BACKSIDE_L2_CACHE
 	select E500MC
 	select E5500
+	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
@@ -784,6 +794,7 @@
 	bool
 	select E500MC
 	select E6500
+	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_47
@@ -814,6 +825,7 @@
 	bool
 	select E500MC
 	select E6500
+	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_47
@@ -1274,6 +1286,10 @@
 	bool "Category E.HV is supported"
 	depends on BOOKE
 
+config FSL_CORENET
+	bool
+	select SYS_FSL_CPC
+
 config SYS_CPC_REINIT_F
 	bool
 	help
@@ -1281,7 +1297,7 @@
 	  required to be re-initialized.
 
 config SYS_FSL_CPC
-	bool "Corenet Platform Cache support"
+	bool
 
 config SYS_CACHE_STASHING
 	bool "Enable cache stashing"